1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to the process of manufacture of polysilicon structures with varying values of resistance and the devices produced by the process.
2. Description of Related Art
U.S. Pat. No. 5,705,418 of Liu for "Process for Fabricating Reduced-Thickness High-Resistance Load Resistors in Four-Transistor SRAM Devices" shows a method of forming polysilicon resistors where an oxide layer is used as an Ion Implantation (I/I) block. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. An oxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer below the oxide layer is reduced. These designated regions are provided to form load resistors. The oxidation resistant layer is then removed. Then, impurity ions are implanted into exposed regions of the polysilicon layer, not covered by the oxide layer, which are designated for forming interconnectors for the memory cell unit.
U.S. Pat. No. 5,514,617 of Liu for "Method of Making a Variable Resistance Polysilicon Conductor for SRAM Devices" shows how to produce resistors using a patterning method with an ion implanation (I/I) process with step areas where variable doping results with higher resistance in the steeper areas than the flat areas, plus heavy doping formed in contact areas by doping through openings in a contact mask.
U.S. Pat. No. 4,643,777 of Maeda for "Method of Manufacturing a Semiconductor Device Comprising Resistors of High and Low Resistances" describes a method of forming resistors in portions of a polysilicon layer with portions covered with mask and the other portions covered with a molybdenum film. Then the molybdenum film is subjected to a silicifying step. The result is that those regions of the polysilicon film located under the molybdenum film have a low resistance, while the regions of the polysilicon film covered by the mask have a high resistance value.
See U.S. Pat. No. 5,622,884 of Liu for "Method for Manufacturing a Semiconductor Memory Cell and a Polysilicon Load Resistor of the Semiconductor Memory Cell" describe a load resistor formed by depositing a polysilicon layer over an insulating layer. The polysilicon layer is ion implanted with dopant and is then masked and etched to form a high resistance load resistor.
In the past, in order to form polysilicon layers with a different resistance in an integrated circuit, the solution has been to modify the area and length of the polysilicon to meet the criteria required. However, that approach increases the cost of manufacturing due to the complex process.